Signal to Noise Ratio (SNR): 65 dBFS (fIN up to 250MHz, 500 MSPS)

ENOB: 10.5 bits (fIN up to 250 MHz, 500 MSPS, − 1.0 dBFS)

SFDR: -78 dBc (fIN up to 250 MHz, 500 MSPS, − 1.0 dBFS)

Integrated input buffer

Excellent linearity
Differential nonlinearity (DNL): ± 0.5 LSB (typical value)
Integral nonlinearity (INL): ± 0.6 LSB (typical value)

Provide LVDS output at 500 MSPS (ANSI-644 level)

1 GHz full power analog bandwidth on-chip reference voltage source without external decoupling

low power consumption
690 mW (500 MSPS) - LVDS SDR mode
660 mW (500 MSPS) - LVDS DDR mode

Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p (nominal value)

1.18 V p-p to 1.6 V p-p, 1.5 V p-p (nominal value)

Optional output data formats (offset binary, binary complement, Gray code)

Clock duty cycle stabilizer

Integrated data clock output with programmable clock and data alignment function