The CD92AD65 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The CD92AD65 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC features a wide bandwidth differential sample-andhold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the CD92AD65 is suitable for applications in communications, instrumentation and medical imaging.A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to 

maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.
The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional onchip dither function is available to improve SFDR performance with low power analog input signals. The CD92AD65 is available in a Pb-free, 48-lead LFCSP and is speci fied over the industrial temperature range of −40°C to +85°C.